1. Field of the Invention
The present invention relates to a method and apparatus for assigning a memory to a multi-processing unit, which assigns memory to the multi-processing unit and changes assigned memory regions, thereby enabling several processing units to use independent and variable memory regions.
The present invention has been deduced from researches carried out as part of Packet-Broadband Convergence Switch Technology Development supported by Ministry of Information and Communication (MIC) and Institute for Information Technology Advancement (IITA) [Project Number: 2008-S-009-01, Title of the Project: Packet-Broadband Convergence Switch Technology Development].
2. Description of the Related Art
Generally, digital devices, such as a Personal Computer (PC), an embedded system, a network processing unit, and a portable device such as a mobile phone, include a micro processing unit, an audio processing unit, an Ethernet controller, a Graphic Processing Unit (GPU), and other various processing units.
The processing units require respective memories with various characteristics. A micro processing unit requires a memory having the largest memory capacity because it controls all digital devices, and a display processing unit or an Ethernet controller require a high-speed memory.
As described above, a variety of processing units built in digital devices include memories suitable for their characteristics, but the memories are not installed in the digital devices according to the number of the processing units. Digital devices are generally designed such that a main memory is shared by several processing units, for convenience of the design and production.
In this case, since several processing units share one memory address region, there is a problem that data corruption is generated for the memory region used by the processing units.
Further, in typical micro processor-based digital devices including processing units, there is a case where the location of an essential memory address region used by a micro processing unit in order to drive an Operating System (OS) and applications is fixed. In the case where defects occur in an address region where an operating system or a specific application is set to operate, which belongs to the memory address region, if the processing unit accesses the address region where the defects have occurred, the processing unit does not operates, so the entire system including the processing unit may stop.
In line with the recent emergence of a high-speed Input/Output (IO) interface, there is an increasing demand for the use of a system memory by a processing unit, provided in an apparatus coupled to the high-speed IO interface. Accordingly, a request for the use of the system memory by a main processing unit (a micro processing unit) and a request for the use of the system memory by the IO Input/Output interface may happen at the same time. Consequently, there is a need for a method of effectively distributing the use of a memory.
For example, when a device on the PCI side to which an Ethernet controller is connected sends an access request for a system memory, if a main processing unit accesses the system memory in order to drive an application, one of the main processing unit and the Ethernet controller must wait or cancel the access request for the system memory.
Meanwhile, in a processing unit in which both a general-purpose processing unit and a network processing unit are embedded, the general-purpose processing unit is generally configured to maintain and manages the entire system, whereas the network processing unit is generally configured to process network packets input or output through a network interface. The processing units performing different tasks as described above can generally have an optimized performance only when the types of memories used according to the characteristics of the tasks are classified. In this case, if several processing units share one memory, not only an optimal performance cannot be obtained, but the number of processing units sharing the memory increases. Accordingly, problems arise because the time that it takes to process the tasks is delayed, and address regions of a memory shared by the processing units may collide against each other.